Matrix Inversion Algorithm: Applications in High Speed MIMO LTE Receiver
Issue:
Volume 1, Issue 1, December 2012
Pages:
1-6
Received:
26 December 2012
Accepted:
Published:
30 December 2012
Abstract: Matrix inversion algorithm acting an important role in MIMO wireless communication.In this paper, we presenta matrix inversion algorithm and it’s applications in the high speed MIMO LTE receiver which is based on floating point DSP. Matrix operations are the most costly computational module within MIMO receivers but a matrix inversion algorithm is very easy to compute and significantly reduce the computational module cost. We will demonstrate the MIMO LTE applications for reducing the module cost by square matrix inversion algorithms.
Abstract: Matrix inversion algorithm acting an important role in MIMO wireless communication.In this paper, we presenta matrix inversion algorithm and it’s applications in the high speed MIMO LTE receiver which is based on floating point DSP. Matrix operations are the most costly computational module within MIMO receivers but a matrix inversion algorithm is ...
Show More
Ghais El Zein. MIMO Hardware Simulator Design for Heterogeneous Indoor Environments Using Tgn Channel Models
Bachir Habib,
Gheorghe Zaharia,
Ghais El Zein
Issue:
Volume 1, Issue 1, December 2012
Pages:
7-16
Received:
9 January 2013
Accepted:
Published:
30 December 2012
Abstract: A wireless communication system can be tested either in actual conditions or by using a hardware simulator reproducing actual conditions. With a hardware simulator it is possible to freely simulate a desired type of a radio channel. This paper presents new frequency domain and time domain architectures for the digital block of a hardware simulator of Multiple-Input Multiple-Output (MIMO) propagation channels. This simulator can be used for Wireless Local Area Networks (WLAN) 802.11ac applications. It characterizes an indoor scenario using TGn channel models. After the description of the general characteristics of the hardware simulator, the new architectures of the digital block are presented and designed on a Xilinx Virtex-IV Field Programmable Gate Array (FPGA). Their accuracy, occupation on the FPGA and latency are analyzed.
Abstract: A wireless communication system can be tested either in actual conditions or by using a hardware simulator reproducing actual conditions. With a hardware simulator it is possible to freely simulate a desired type of a radio channel. This paper presents new frequency domain and time domain architectures for the digital block of a hardware simulator ...
Show More